Akshatha Deshpande
MS ECE @ NC State | Open to Performance Architect, Digital Design & Verification Roles | RTL, SystemVerilog, C++, SoC Modeling | Ex-Havells
- Role
- Design Engineer at Western Semiconductor
- Location
- Raleigh, NC, US
- LinkedIn followers
- 500 followers
About Akshatha Deshpande
Hi, I’m Akshatha, a Master’s student in Computer Engineering at NC State …
Experience
Design Engineer
Jun 2025 — Present
Working on RTL design of a memory controller block for a RISC-V CPU on a 40nm node. The controller interfaces with HBM3 memory.I am collaborating with senior engineers to integrate the controller within a SoC architecture including arbitration, interconnect, and peripheral interfaces.Analyzing design trade-offs and contributing to architecture discussions, applying a performance-focused mindset to improve throughput and latency
Education
Alva's Institute of Engineering and Technology
Bachelor of Engineering - BE
2017 — 2021
North Carolina State University
Master of Science - MS
2023 — 2025
Narayana e-Techno School
10th Grade
Narayana Junior College - India
MPC
2015 — 2017
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