Ch Ajit Kumar Patro
Layout Design Engineer at Intel Corporation
- Role
- Layout Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ch Ajit Kumar Patro
Technical Standard Cell Layout Design Engineer with 4+ years of experience at Intel…
Experience
Layout Design Engineer
Sep 2021 — Present · IN
Layout Design Engineer – Standard CellsWorking on advanced technology nodes with expertise in physical design, verification, internal flow development, and team enablement.Key Responsibilities:• Designing standard cell layouts for the latest process technologies(intel 3, intel 20A,intel 18A, intel 14A)• Proficient in industry tools: Cadence Virtuoso, Synopsys Custom Compiler• Debugging DRC, LVS, and Reliability Verification (RV) issues across multiple libraries• Managing and executing central runs for production libraries• Analyzing new design rules from PDK releases and delivering impact assessments to the library team• Contributing to internal flow development for standard cell design tailored to Intel’s ecosystem• Developing custom checks and providing design logic to ensure high-quality, customer-focused standard cells• Leading onboarding and ramp-up of new team members, guiding them towards successful contribution in production work• Owning final QA for standard cell libraries, including timestamp verification, flow validation, view correctness, and delivering detailed QA reports within tight post-release timelines• Engaged in R&D to evaluate evolving design constraints and report implementation insights
Education
Saraswati sishu Vidya mandir, Neelakanta nagar
Matriculation, All subject
2014 — 2015
Silicon Institute of Technology (SIT), Bhubaneswar
Bachelor of Technology - BTech, Electronics and Communications Engineering
2017 — 2021
Saraswati vidya mandir, Neelakanta nagar, Berhampur
12th, PCM
2016 — 2017
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