Anandkumar Mahadevan Pillai

Memory Physical Design Engineer at Intel Corporation

Role
Component Design Engineer at Intel
Location
San Jose, CA, US
LinkedIn followers
500 followers

About Anandkumar Mahadevan Pillai

Current graduate student pursuing Masters in Electrical Engineering at University of Minnesota - Twin Cities with research interests in Digital/Mixed-Signal Design, FPGA-based design and Computer Architecture. Presently, seeking internships opportunities in these fields for summer 2016.Technical Skills:Expertise in: Digital logic design (RTL, gate and spice level), digital logic synthesis and test bench developmentASIC design flow and custom layout design Analog and digital VLSI circuit design and experience in designing circuits like OP-AMP, current mirror, data convertersCache design, replacement strategies, dead block prediction strategiesFPGA based hardware/software design and debugProgramming languages like Verilog HDL, Verilog-A, C, C++ and good knowledge in Perl scripting languageEmbedded system designXilinx core generators. Experience in using IP cores such as ZYNQ processor, clock wizard, AXI GPIO and block RAMEDA Tools such as: Cadence (Virtuoso, Spectre, Layout XL), HSPICE, Synopsys CosmoScope, Xilinx ISE (Core Generator, Plan Ahead and Chipscope), Xilinx Vivado, Mentor Graphics ModelSim, SimpleScalarGood understanding of device physics and sub-micron device fabrication flow

Experience

  1. Component Design Engineer

    Intel

    Jun 2017 — Present · Portland, OR, US

Education

  • University of Minnesota

    Master of Science (M.S.), Electrical and Electronics Engineering

    2015 — 2017

  • Amrita Vishwa VIdyapeetham

    Bachelor of Technology (B.Tech.), Electronics and Communication Engineering

    2010 — 2014

Skills

  • Xilinx
  • Unix
  • C
  • Programming
  • Xilinx Ise
  • C++
  • Hspice
  • Simulations
  • Spice
  • Field-Programmable Gate Arrays (Fpga)
  • Analog Circuits
  • Matlab
  • Cadence Virtuoso
  • Digital Circuit Design
  • Cadence Spectre
  • Perl
  • Embedded Systems
  • Cadence Virtuoso Layout Editor
  • Mixed-Signal Ic Design
  • Circuit Design
  • Verilog-a
  • Very-Large-Scale Integration (Vlsi)
  • Microsoft Office
  • Vlsi
  • Modelsim
  • Layout Design
  • Cosmosscope
  • Verilog
  • Fpga
  • Asic

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Anandkumar Mahadevan Pillai — Component Design Engineer at Intel in San Jose, CA, US | Unifers