Abhishek Jaiswal

About Abhishek Jaiswal

Experienced professional with 20 years of experience in Micro-architecture (Memory management, Switches, AR/VR), SOC/IP Design Implementation. Expertise in driving the development of chips and products from concept through to netlist. Proficient in RTL design, formal verification, linting, timing analysis, and silicon validation. Highly skilled in using Synopsys and Cadence EDA tools, with strong programming capabilities in Verilog, SystemVerilog, Perl, C, C++, and Python. Demonstrated ability to collaborate across teams and deliver high-quality solutions.Specialties: Verilog, System Verilog, Certitude, Formal Verification, OVA and System Verilog Assertions, C, C++

Experience

1. Building Scale up out Solution

   NVIDIA

   Oct 2025 — Present

Education

• Indian Institute of Technology, Kanpur

  B-Tech, Electrical

  2001 — 2005

Skills

• Rtl Coding
• Testing
• C
• Integrated Circuit Design
• C++
• Simulations
• Rtl Design
• Soc
• Debugging
• Formal Verification
• Digital Design
• Asic
• Vlsi
• Static Timing Analysis
• Eda
• Verilog
• Systemverilog
• Algorithms