Akhileshwar Kumar
Soc/RTL Design Engineer at Intel Corporation
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Akhileshwar Kumar
12+ years in rtl/soc Design(Simulation/Emulation/validation/soc) having very good hands on experience in rtl/soc design using Verilog and system Verilog. I worked on altera video IP, meggitt/utas/parker aerospace IP, SATA3.0, MIPI_CSI2_CCI and AMBA_APB protocol and also knowledge of RISC, UART and I2C.Recently from last 8+ years I am working on SOC/SS Design/Integration at Intel with specialty in CLOCKING and CDC.
Experience
Soc Design Engineer
Nov 2016 — Present · IN
Education
CDAC
PGDEVD, VLSI
2010 — 2011
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
ICFAITECH DEHRADUN
B.TECH, ECE
2006 — 2010
Skills
- Linux
- Open Verification Methodology
- Eda
- Vhdl
- Simulations
- Debugging
- C++
- Emulation
- Network on Chip(Noc)
- Digital Electronics
- Tcl
- Verilog
- Very-Large-Scale Integration (Vlsi)
- Application-Specific Integrated Circuits (Asic)
- Rtl Design
- Logic Synthesis
- Uvm
- System Verilog
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