Akhilesh Sharma
Senior Engineer @Analog Devices
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WORK HISTORY
Senior Engineer @Analog Devices
Bengaluru, IN
Working on the Formal Verification for Multi die SoC for AI applications-> Complete end-to-end ownership for formal verification of the switch matrix of the SoC-> Successfully deployed Sentence Transformer based simulation logs binning solution on ADI\'s HPC infrastructure to enable DV engineers across ADI to be able to do intelligent binning of of logs generated from the regression for faster debug cycles-> Side Projects/ Achievements :* Got runners up position out of 24 teams in a Data Hackathon where we have to propose data monetization techniques for ADI. I proposed the idea of creating Data-as-a-service model on top of the SOC platform for PV inverters giving insights to customers by leveraging weather models for demand forecasting and smart management of solar inverters. Also proposed AI model for predicting latent faults for functional safety of PV inverters.* Got runners up position out of 9 teams in ML challenge across ADI to create an AI/ML based end-to- end solution for regression logs binning for faster debug of DV issues. The solution was very cost- effective and scalable also as it was designed to run on a CPU completely avoiding high cost of GPU infrastructure to run an AI based solution.
EDUCATION
Birla Institute of Technology and Science, Pilani
Master's degree, Artificial Intelligence and Machine Learning
Thapar Institute of Engineering & Technology
Bachelor of Engineering - BE, Electronics and Communication
ABOUT AKHILESH SHARMA
Design Verification Engineer | AI Hardware & Multimedia IP/ SOC Verification | Pursuing Masters in AI and ML. Hello! I\'m Akhilesh Sharma, a Lead Verification Engineer with over 5 years of experience at Samsung Research India and STMicroelectronics. Specializing in SOC/IP level verification, I focus on AI/ML hardware and multimedia IPs, leveraging Generative AI to revolutionize verification processes.Why I standout:Technical Acumen: Proficient in System Verilog, UVM, C, C++, Python, and key protocols like AXI, AHB, and APB. Skilled with Xcelium, VCS, Verdi, my toolkit is primed for complex verification challenges. I have experience building SV-UVM based testbench from scratch. Collaborative Excellence: Known for leading cross-functional teams to success, I\'ve driven crucial IP verifications for flagship products, emphasizing quality and efficiency.AI-Driven Verification Strategy: Utilizing Generative AI, I enhance test plan efficiency and coverage, accelerating development and ensuring thorough scenario coverage.Leadership & Mentorship: I mentor juniors and lead teams through intricate projects, fostering innovation and growth.Continuous Learning: Committed to pushing the boundaries of verification methodologies with a proactive, innovative approach.I am keen on applying my IP and SOC verification expertise, augmented with Generative AI insights, to address new challenges and advance next-gen technologies. Looking to collaborate with professionals passionate about semiconductor industry innovation.Connect with Me!For insights or collaborations in design verification and AI, reach out via LinkedIn or email at a••••••••@gmail.com.
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