Akhil Veeranala
- Role
- Pre Silicon Verification Engineer at Intel
- Location
- Sacramento, CA, US
- LinkedIn followers
- 500 followers
About Akhil Veeranala
Working for Intel, Folsom in the NSG 3D NAND Design Verification team. Graduated from the…
Experience
Pre Silicon Verification Engineer
Dec 2018 — Present
NSG (Non-Volatile Memory Solutions Group) – 3D NAND Pre Silicon Verification Enginner o Verification • Worked on verification of Intel’s first independent 3D NAND 130’s QLC product using UVM & Verilog TB. • Mixed Signal verification environment with LDOs, DACs, Charge Pumps, Oscillators, digital logic, custom memories, high speed datapath logic and HV/LV devices. • Developed directed & constrained random tests for feature based on exhaustive RTL code test plan for memory chip with SLC/TLC/QLC capability. • Automated validation by developing SystemVerilog Assertions and worked closely with design team to resolve firmware bugs. • Used advanced sequences in UVM Environment to develop quality tests and deliver on time. • Resolved numerous failed tests and debugged using all collaterals – firmware, waveform and log files to report bugs raised due to RTL Design, firmware or tests. o Post Silicon & Lab • Working with Product Engineering and DV teams for Silicon probe Simulations. Debugging of any Post Silicon Algorithm/CMOS design issues and providing the efficient design fix. • Involved in Lab experiments to analyze the performance of NAND component and feature support to qualify the component for product.
Skills
- Eda
- C++
- Integrated Circuit Design
- Java
- Verilog
- Cadence Spectre
- Optimization
- Microsoft Excel
- Circuit Design
- Cadence
- Vhdl
- Sql
- Html
- Integrated Circuits (Ic)
- Cadence Virtuoso Layout Editor
- Linux
- Modelsim
- Application-Specific Integrated Circuits (Asic)
- Microsoft Sql Server
- C
- Very-Large-Scale Integration (Vlsi)
- Computer Architecture
- Microsoft Office
- Databases
- Cadence Virtuoso
- Matlab
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