Ashik Ghona

About Ashik Ghona

PROFILE SUMMARY:Overall 14+ years of VLSI Industry experience in ASIC Front End Design Verification of IPs and SoCs.• Executed, contributed and eyewitness of numerous tape outs till date in Server, Mobile space• Hands on experience on Power Aware simulations and Gate Level simulations (GLS) of complex Mobile SoCs.• Experience with System Verilog + C based SoC level Mobile SoC verification.• Experience with UVM based block level environment bring up having multiple agents and interfaces.• Strong experience with Test planning, Constraint Random, Directed and Corner Testcases identification and development.• Experience with Code Coverage and Functional Coverage report generation, analysis and improvement, Coverage closure and Coverage waiver.• Extensive experience in Debugging, Bug reporting and Bug fix validation, Regression run.• Strong hands on experience with AMBA-AXI,AHB,APB protocol based Modem and Mobile SoC verification.• Experience of collaborating with geographically diverse multi-site and multi-functional teams.• Ability to technically mentor junior team members.Languages, Protocols, Methodology Exposure : Languages: Verilog, System Verilog (SV)Protocols : AMBA AXI, AHB, APB, OAM_Y1731, PTP_1588, Ethernet MAC, USB3Processors : ARM Cortex, Tensilica LX7Methodology : Universal Verification Methodology (UVM), Scripting Languages : Perl, Shell

Experience

1. Soc Low Power Verification Lead

   Google

   Jul 2021 — Present · Bengaluru, IN

   Contributing on cutting edge Tensor SoCs verification which powers up Google Pixel phones every year.

Education

• Sadeepani School of Advanced System Design

  Professional Development course in VLSI system design and verification, Semiconductor Technology

  2011 — 2012

• Dharmsinh Desai University

  BE, Electronics & Communication

  2007 — 2011

• BVB's Narmada Vidyalaya

  Higher Education, -Where I had learnt Physics,Chemistry,Maths,English,Hindi,Gujarati,Drawing,Sports,Social Studies

  1992 — 2007

Skills

• C++
• Soc
• Xilinx Ise 13.4
• Shell Scripting
• Physical Design
• Debugging
• Arm7
• Spartan 3e
• Rtl Coding
• Regression Testing
• Xilinx
• Systemverilog
• Vlsi
• Questasim
• Formal Verification
• C
• Arm
• Modelsim
• Functional Verification
• Oop
• Unix Shell Scripting
• Make Scripting
• Uvm
• Amba Ahb
• Vim
• Fpga
• Asic
• Digital
• Testplan Devlopment
• Unix
• Apb
• Rtl Design
• Mixed Signal
• Microcontrollers
• Cmos
• Verilog
• System Verilog
• Universal Verification Methodology (Uvm)
• Assertion Based Verification
• Microprocessors