Akash Mallula

Vlsi Physical Design Engineer @Coforge

US

Experienced in RTL integration, synthesis, and full physical design flow from netlist to GDSII. Proficient in resolving connectivity issues, optimizing for area, power, and timing using tools like Design Compiler and IC Compiler. Skilled in STA, physical verification (LVS/DRC), and ensuring design equivalence and readiness for tape-out.Resolved over 300 timing violations using Synopsys PrimeTime and updated SDC constraints, enabling five 14nm blocks to meet timing across both functional and test modes under Multi-Mode Multi-Corner analysis.Improved power integrity by 22% by optimizing decap cell placement and enhancing power grid coverage based on static IR drop and electromigration (EM) analysis using Ansys RedHawk.Reduced DRC and LVS failure rates by 35% by updating LEF/DEF views, correcting layout geometries, and validating signoff readiness using Calibre in the Cadence Innovus integration flow.Developed reusable shell and TCL scripts for STA reporting, saving over 20 engineering hours per week and enhancing consistency across timing review reports and closure documentation.Delivered first-pass RTL-to-physical handoff success for four SoC blocks by aligning floorplan boundaries, clock constraints, and physical views in close collaboration with RTL and backend design teams.

CMR College of Engineering & Technology

Bachelor of Technology - BTech

University of Massachusetts Amherst

Master of Science - MS