Akash I Girevvagol

Research Assistant @Fraunhofer IIS

Dresden, DE

1) Conducting research on optimizing Large Language Model (LLM) inference on RISC-V–based platforms, with a focus on transformer architectures such as LLaMA 70B.2) Analyzing computational requirements, DRAM bandwidth utilization, and memory bottlenecks in transformer Q/K/V processing pipelines.3) Developing and simulating memory hierarchy optimizations in gem5, including cache tuning, DRAM type comparisons (DDR3, DDR4, DDR5), and prefetching mechanisms.4) Investigating hardware/software co-design strategies to improve execution time, reduce memory latency, and increase inference throughput for AI workloads on embedded systems.5) Exploring cycle-accurate performance modeling, including DRAM access patterns, compute cycle estimation, and matrix multiplication tiling strategies.

Presidency University Bangalore

Bachelor of Technology, Electrical, Electronics and Communications Engineering

Sri Taralabalu Jagadguru College of Physical Education, Davangere.

Higher education, PCMB ( Physics Chemistry Mathematics Biology )

Technische Universität Dresden

Master's degree, Nanoelectronic Systems

Ramanashree English School

SSLC