Akash B Srinivasa

About Akash B Srinivasa

Hi there!I am Akash. A dynamic and versatile IC designer, programmer and EDA developer. Always strive to transcend my mastery and adroitness to build complete product across every aspects of IC design. Result oriented individual with passion to create exceptional value to my organization.In addition to IC design, using some of the learnings of statistics/probability theories to account for manufacturing variations in IC design, I have also developed expertise in Quantitative Finance, Algorithmic Trading/Investing and have developed various fully automated proprietary trading and investing systems with statistical edge, running on cloud (AWS EC2 and Oracle cloud) coded using REST APIs, Python, PyTorch for ML, Webdrivers, Websocket programming with experience in handling SQL/NoSQL databases.Highlights of my professional experience:• 14+ years of expertise in various aspects of Integrated Circuit Design, Verification and Automation with specialties in Embedded Custom and Compiler Memory Development from 180nm to 2nm process nodes.• Worked on developing High throughput and Energy efficient In-memory computing architectures and circuits for Deep Neural Networks and AI applications.• Experienced in leading teams/platforms for full memory development life cycle from specifications to tapeout on various High Speed and High Density SRAM (Register Files, Single, Dual and Multi-Port (4, 6 and 8 port)) and ROM (Fuse or Via Programmable) architectures with varieties of design features. • Experienced in varieties of numerical techniques and methodologies to develop Variation-tolerant, Reliable Memory designs, Efficient-High quality EDA tools.• Experienced in Yield estimation techniques and Reliability analysis of complete Memory designs (EM/IR, BTI and HCI Guard bands).• Experienced in leading Pre-sales studies of various memory architectures with customer interactions.• Proficient in developing EDA solutions using Perl, Perl-Tk, SKILL and Shell scripts. Experienced in developing multiple aspects of Memory characterization flows. Bench-marked and Proposed several Curve Fit algorithms for compiler level char to improve its quality and efficiency.• Experienced in I/O (GPIO, SSTL, HSTL and LVDS) and ESD circuit designs. • Possess sound knowledge and keen interest towards Device Physics, FEOL and BEOL variability issues, Back of the Envelope techniques in varieties of SPICE Algorithms and BSIM device modelling.

Experience

1. Principal and Staff Design Engineer

   Arm

   Apr 2019 — Present · Bengaluru, IN

   Highlights- Currently doing research on Energy efficient approaches to optimize the Cache Access pipelines from System Level caches to CPU Registers for future arm cores and developing multiple custom circuit and methodology implementations- Worked as lead for 2nm High Density bitcell based memory with unique power mode features for achieving ultra low leakage at L3 cache level- Worked on scratch development of Custom High speed Multiport memories with multiple read and write port configurations for next generation of arm processors, which were earlier handled at RTL level- Worked as lead for High speed, High density and Dual port custom/compiler memory developments in 3nm and 5nm GAE technologies across multiple foundries with support for wider range of voltage domains with robust assist circuits- Worked on developing High throughput and Energy efficient In-memory computing architectures and circuits for Deep Neural Networks and AI applications- Contributing as a key member of Memory Architecture and Circuits committee within Arm\'s physical design group- Published a research paper titled \"High speed pseudo-write assist circuits for SRAM to tackle high metal resistance in 7nm technology and beyond\" in DAC 2019- Filed multiple patents on Assist circuits especially for sub 10nm technologies

Education

• B. M. S. College of Engineering

  B.E, Telecommunication

  2007 — 2011