Akash Apasangi

Sr Director R & D Interface IP

Role
Senior Director R & d at 新思科技股份有限公司
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
Research & DevelopmentView LinkedIn profile

About Akash Apasangi

Currently leading the 224G and 112G Serdes PHY IP teams at Synopsys. Leading digital…

Experience

  1. Senior Director R & d

    新思科技股份有限公司

    Feb 2024 — Present · Bengaluru, IN

Education

  • K.E. Board's High School

    SSLC

    1990 — 1997

  • SDM College of Engineering & Technology

    BE

    1997 — 2003

  • RMIT University

    Master of Engineering

    2003 — 2004

Skills

  • Formal Verification
  • Project Planning
  • Usb
  • Ieee1149.6
  • Soc
  • Scrum
  • Physical Design
  • Debugging
  • Application-Specific Integrated Circuits (Asic)
  • Jtag
  • Dft
  • Project Management
  • Logic Synthesis
  • Ieee1149.1
  • Mixed Signal
  • Semiconductors
  • Power Management
  • Static Timing Analysis
  • Vhdl
  • Low-Power Design
  • Vlsi
  • Functional Verification
  • Fpga
  • Timing Closure
  • Project Management Body of Knowledge (Pmbok)
  • Asic
  • Rtl Design
  • C
  • System on a Chip (Soc)
  • Front-End
  • Systemverilog
  • Ncsim
  • Verilog
  • Analog
  • Upf
  • C++

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Akash Apasangi — Senior Director R & d at 新思科技股份有限公司 in Bengaluru, KA, IN | Unifers