Akarsh P K
RTL Designer||VHDL||Verilog||Hardware Design||Front end synthesis||FPGA DESIGN||Lint||CDC||SOC_Integration
- Role
- Asic Design Engineer at Ericsson
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Akarsh P K
Working at Mirafra, having 5+ years of industrial experience. I have acompleted BE in Electronics and Communication.I am actively seeking for an opportunity in front end design/RTL Design/Micro Architecture Design to enhance my analytical and technical skills. I have worked on following tasks.1. RTL Design 2. Debug Support for Verification Team 3. RTL/IP/Subsystem Integration 4. Quality Checks for RTL ( Lint, CDC etc) 5. Logical equivance checks (Formality )Technical Skill Sets:EDA Tools: Xilinx Vivado, Xilinx iSE, DC complier, Formality, Spy Glass.Hardware Description Languages: Verilog, VHDL.Scripting Language: TCL.Synthesis tool : DC_Compiler, Synplify Pro, Caliber.Hardware Platforms: FPGA, Microcontrollers, ASIC front end synthesis OS Platforms: Linux, Windows.Area of Interest: RTL Design and Micro-Architecture DesignDigital DesignStatic Timing AnalysisContact Details:1. Current LinkedIn Profile.2. Email: a••••••••@gmail.com
Experience
Asic Design Engineer
Nov 2025 — Present · Stockholm County, SE
Education
SHREE MADHWA VADIRJA INSTUTE OF TECHNOLOGY & MANAGEMENT
Bachelor of Engineering, Electrical, Electronics and Communications Engineering
2014 — 2018
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.