Ajnesh Singh

About Ajnesh Singh

Specialties: Multi Die Solution(3DIC) End to End Implementation (Design Planning, Implementation and 3DIC Sign off including -Thermal Analysis, Signal Integrity,Power Integrity, Extraction-STA, EMIR 2DIC Design and Implementation - Synthesis(DC,FC),Full Chip/Section/Partition Physical Design(FloorPlanning,Placement,CTS,routing.ECO ),Primetime, Physical Verification(DRC,LVS), IR Drop Analysis, IP physical integration(PLL,ADC,DAC,FLASH,OSC ) Special routes. IO Ring creation

Experience

1. Principal Engineer

   新思科技股份有限公司

   Feb 2025 — Present · Bengaluru, IN

Education

• Indian Institute of Technology, Roorkee

  Master of Technology (MTech), Electronics & Communication

  2009 — 2011

Skills

• Debugging
• Design Compiler
• Clock Tree Synthesis
• Physical Verification
• Logic Design
• Cmos
• Algorithms
• Physical Design
• Tcl
• Lvs
• Cadence
• Ic
• Eda
• Drc
• Soc
• Timing Closure
• Floorplanning
• Static Timing Analysis
• Digital Electronics
• Asic
• Primetime
• Compilers
• Logic Synthesis
• Cadence Virtuoso
• Ams
• Vlsi
• Integrated Circuit Design
• Semiconductors
• Phsical Design
• Analog Circuit Design
• Low-Power Design
• Verilog