Ajesh K Madhavan
Physical Design Lead at Intel Corporation
- Role
- Senior Physical Design Engineer at Intel
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Ajesh K Madhavan
Physical Design Lead at Intel CorporationSpecialties: PNR, STA, Synthesis and signoff in Low Power and High Frequency Designs in various advanced technology nodes.
Experience
Senior Physical Design Engineer
Jan 2021 — Present · Bengaluru, IN
Education
Vellore Institute of Technology
M.Tech, VLSI Design
2006 — 2008
Cochin University of Science and Technology
B-TECH, ECE
Skills
- Clock Tree Synthesis
- Power Analysis
- Static Timing Analysis
- Primetime
- Eda
- Soc
- Asic
- Low-Power Design
- Timing Closure
- Physical Design
- Functional Verification
- Floorplanning
- Tcl
- Physical Verification
- System on a Chip (Soc)
- Formal Verification
- Very-Large-Scale Integration (Vlsi)
- Lvs
- Cadence
- Drc
- Vlsi
- Synthesis
- Logic Synthesis
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