Ajeetkumar K Dani
IBM assigned to EY | BIG FOUR | HR DEPT.
- Role
- Process Associate-l & d at IBM
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ajeetkumar K Dani
Hi! I’m Ajeetkumar, an RTL & Design Verification trained fresher with hands-on experience in Verilog, SystemVerilog, UVM, and industry tools like QuestaSim, ModelSim, Vivado, Quartus Prime, Cadence Virtuoso, and Calibre. I also have strong exposure to Analog & Mixed-Signal Layout in 40nm CMOS, including DRC/LVS/ERC, LDO/BGR layouts, and DSM concepts.I enjoy working on digital design, verification, and analog layout, and I’m comfortable in Linux environments with GitHub/SVN and Python scripting. I’m looking for opportunities in RTL Design, Functional Verification, or Analog Layout where I can apply my skills and grow in the semiconductor domain.
Experience
Process Associate-l & d
Jan 2026 — Present · Bengaluru, IN
Education
Naryana Pre-University College, BALLARI
PCMC
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