Ajeet Singh Lowanshi
Design Engineer II (STA) at AMD
- Role
- Design Engineer Ii at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Ajeet Singh Lowanshi
Experienced with RTL Development for FPGA | Design Creation and Migration | Debugging and Fixing Implementation |IP Handling and Upgradation (DDR, CMAC, PCIe)- Expertise in Static Timing Analysis and timing closure- Design Analysis and benchmarking for QoR improvement- Strong knowledge of Digital Electronics- Good hand in TCL and python Scripting for Automation- Experienced with Xilinx-vivado, Altera-Quartus, Cadence-Innovus, Cadence-virtuosoM.Tech from NIT Raipur (2017-19), worked as a Intern at Si2 chip Technologies as Physical Design EngineerM.Tech projects related to Device modelling, Integration of Power Gating and Clock Gating, Cordic, Systolic array, FSM, MAC, e.t.c.Publications :\"An Effective Charge Plasma based Semi-superjunction MOSFET\", 2nd International conference on Systems Computation Automation and Networking,(ICSCAN 2019), March
Experience
Design Engineer Ii
May 2024 — Present · Hyderabad, IN
Education
National Institute of Technology Raipur
Master of Technology - M.Tech
2017 — 2019
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