Ajay Balu Kuzhively

About Ajay Balu Kuzhively

Engineer specializing in Digital VLSI design, actively seeking full-time opportunities in the field of Digital/Hardware/SoC/ASIC or Physical design. I have experience in Python, UNIX, Perl, BASH, and TCL scripting.Currently Working as a Stdcell Characterization Engineer at Qualcomm, San Diego->3nm Standard cell Tech lead for TSMC foundry. Successfully taped out chips for 0.9 PDK, 1.0 PDK, and 1.1 PDK by defining methodology/modeling changes and aligning with the foundry, tool vendor, and internal teams->Owner of Slew and load methodology deliverables for all library characterizations. Reduced the deliverable time by 60%(reduced run time with an end-to-end script written in Python). Analysis of Standard cells, layout, and methodologies to improve PPA->Methodology alignment, spec creation, review, and debugging for MC vs LVF reports, Voltage scaling reports, MIS reports, and CLS Reports->Developed Cell models for new and existing Standard cells. Performed functional and formal verification for new and existing standard cells->Collaborated closely with cross-functional teams to address library cell issues, sigma variation analysis, and quality control. Enhanced existing methodologies to improve timing, power, area, and reliability.MS Thesis on Quantization and Evaluation of AI Algorithms for Hardware Acceleration.o A low-precision sparse DNN model was developed for the reconstruction of the image.o Binarize a part of the layers to decrease the number of weights and activations on the chip to improve the accuracy.o Reclaiming the accuracy for more complex datasets with layer-wise quantization.Selected Coursework- VLSI design- Computer Architecture 2- Neuromorphic Computing and Hardware Design- Hardware Acceleration and FPGA Computing- Constructionist approach for Microprocessor Design- Digital Signals and Circuits- Analog Integrated Circuits- Advanced Analog Integrated Circuits

Experience

1. Physical Design Engineer

   Intel

   Mar 2024 — Present · Chandler, AZ, US

   Intel 14A test chip partition owner. The test chip contained a voltage regulator IP and a PLL generating a 4.8 GHz clock, with an additional 1.4 GHz clock feeding into the partition. The clock tree structure for both clocks was handcrafted.*Successfully signed off Timing, Layout Verification, IR and thermal flows for the partition. The test chip was taped out ahead of schedule.*Owned the script to generate min-max timing windows for various IPs using lib compare and timing budget details provided by the PV team.*Collaborated with the RTL SoC team on UPF generation for the Intel 14A test chip. Developed an end-to-end UPF generation script to produce UPF files from RTL team specifications.*N2P test chip partition owner. The test chip was successfully taped out, containing IPs from internal teams and clients.*Owned ESD, LVS, and PERC runs across all partitions for the N2P test chip. Collaborated with methodology teams to efficiently implement ESD designs within the test chip.*Owned Timing, Layout Verification, IR and thermal sign-off for IO partitions of the N2P test chip.*Collaborated with Frontend and TFM teams to ensure successful tapeouts for the TSMC N2P test chip.*Currently part of the PV team for DDR Gen2, overseeing day-to-day activities including the creation of PV models and debug support for partition owners.*Currently owns the Calibre and PTPX workflows for the DDR Gen2 group. Implemented the *CalibreLite tool methodology to streamline debug, review, and waiver filing processes for Caliber. Also tested and finalized the finale flows for the DDR Gen2 group.

Education

• Arizona State University

  Master of Science - MS, Analog and Mixed Circuit Design

  2019 — 2021

• National Institute of Technology Calicut

  B.Tech, EleElectronics and Communications Engineering

  2014 — 2018