Ajay Thiriveedhi
- Role
- Engineering Manager at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
Experience
Engineering Manager
Mar 2021 — Present
Leading and Managing low power verification of several SoCs
Skills
- Tcl
- Physical Design
- Low-Power Design
- Fpga
- Rtl Design
- Asic
- Semiconductors
- Timing Closure
- Functional Verification
- Static Timing Analysis
- Ic
- Formal Verification
- Verilog
- Soc
- Debugging
- Systemverilog
- Vlsi
- Eda
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