Ajay Rasquinha
Dft Methodology @NXP Semiconductors
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WORK HISTORY
Dft Methodology @NXP Semiconductors
Austin, TX, US
EDUCATION
ST GERMAINS BOYS HIGH SCHOOL
ICSE
St.Aloysious
12
Bangalore University
BE, TELECOMUNICATION
SKILLS
ABOUT AJAY RASQUINHA
Professional Synopsis A dynamic professional with 20+ years of comprehensive experience in DFT/Product Engineering. Product Engineering Lead for (2M/5M) CMOS Image sensor (Mixed Signal Design). Logic and Memory failure Diagnosis and yield improvement. Analog DFT. DFMEA implementation for Automobile parts. ASIL implementation for Mixed Signal design. Memory Test Methodology and automation. DFT lead for test chips and automotive infotainment SOC. CAD development (perl/tcl/shell) for memory BIST verification and pattern generation. Worked with Mentor and Synopsys tools for SCAN/MBIST insertion verification pattern generation and failure diagnosis. RTL coding for DFT modules.Key SkillsDesign For Test (DFT) SCAN (Stuck-at/Transition/Iddq/Cell Aware) MBIST IP Test BSCANProduct Engineering Bench Validation/Characterisation (Wafer/package) Probe test. Yield analysis and management.o SCAN/MBIST failure diagnosis.o Support PFA/EFA and provide feedback to foundry. Reliability/Product Qualification Test. Production Ramp support. RMA( Customer Return Material ) support. Application engineering support for customer queries.ToolsSCAN Tessent Testkompress Yield InsightMBIST Tessent MBIST Synopsis STAR memory testPost-Silicon Failure Diagnosis Tessent Silicon Insight (Memory) Tessent Yield Insight (Logic)Statistical Data Analysis dataConductor by PDF solutions (formerly Syntricity) dataPOWER by PDF solutions JMP
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