Ajay Pratap Singh
Soc Verification @Socionext US
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WORK HISTORY
Soc Verification @Socionext US
Milpitas, CA, US
SOC level verification, Block level verification, Arm, SystemVerilog, C, SVA, Verilog, VCS, UVM.
EDUCATION
National Institute of Technology Kurukshetra
MTech, Electrical Enginering
Amravati University
BE, Electronics and Communications Engineering
SKILLS
ABOUT AJAY PRATAP SINGH
Summary: Fifteen plus years of strong experience in various stages of ASIC development. Specialties: Broad level technical expertise in functional verification, SOC, Processors, Wireless, Networking and Communication domain. SystemVerilog/OVM/UVM/Specman methodologies Constrained random testbenches Formal verification, Assertions, Gate sims. Hands-on management. Functional verification methodology development Managing matrix organization Global team development and management Driving quality improvements, planning, scheduling, execution and efficiency.Skills/Tools: Hardware Description Languages: Verilog Programming languages: E Language, SystemVerilog, C, Assembly Language programming for MIPS, 8085/86 Scripting Languages: Perl Simulation Tools: Cadence’s Incisive platform, Synopsys VCS Simulator, Questa Linting Tools: Verilint, Spyglass Verification Tools: Varisity’s Specman, Vmanager, 0in Coverage Tools: IMC, Covermeter, Surecov Debugging Tools: Simvision, Verdi FPGA: Xilinx\'s Vivado, Altera\'s Max+plus II, Xilinx Synthesis Tools: Synopsys’s Design Analyzer Behavior Modeling Tools: Archgen, Application specific virtual prototype Backend Tools: Cadence’s Preview (Opus) Operating Systems: Linux, Solaris, Windows
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