Ajay Kothari

About Ajay Kothari

hands on 6+ years of experience in IP(intellectual property) implementation from PnR netlist to GDSII on 16nm to 3nm technology node ranging.Experince with EDA tools : Synposys tools icc/icc2/icv/icc2_lm_shells/redhawk/primetime/starrc Expertise in PNR flow development/ floor-planing/ placement and timing analysis/ CTS and MSCTS flow development/ reduce latency and skew experiment /static timing analysis / DRV fixing / DRC fixing Experienced in IP implementation :DDR4/LPDDR5 on 16nm technolgyHBM2e /1.6 G functional frequency and 3.2G frequency PCLK clock on 7nm technologyHBM2e / 1.8 G functional frequency and 3.6G frequency PCLK clock on 7nm technolgyHBM3 /1.8 G functional frequency HBM3 updated PDK on 6nm technology nodeongoing Porject UCIe on 3nmi have good experienced knowledge in PNR flow development / timing analysis / CTS and MSCTS / static timing analysis and fixes / FEOl DRC and BEOL DRC analysis and fixes / EM- IR analysis and fixes.familiar with language : TCL, proficenet in perl /awk/sed/make, shell scripting i have good debugging and problem solving skills.Education Qualification :B.E in electronics engineering (20••••16), B.V.M engineering college in V.V.nagar Anand with 7.92 CGPA.+Email-ID : a••••••••@gmail.com+Contact No :+91••••••••20i am always willing to learn new things and work on challanging taks.

Experience

1. Principal Engineer

   Cadence

   Jan 2026 — Present · Pune, IN

Education

• B.V.M Engineering collage

  B.E, electronics engineering

  2012 — 2016

• Gujarat Technological University (GTU)

  Bachelor of Engineering (B.E.), electronics engineer

  2012 — 2016

Skills

• Orcad
• Regular Expressions
• Sta
• Perl
• Learning Encounter Tool
• Verilog Hdl
• Lynx
• Ndm Lib Preparation
• Synthesis
• Physical Design
• Linux Operating
• Synopsys Prime Tool
• Placement&Routing
• Floorplaning
• Starting Phase of Icc2
• Synopsys Dc Compiler
• Tcl
• Clock Tree Synthesis
• Basic C-Language
• Syonopsys Icc Compiler