Ajay Chandrasekhar
Logic Design Methodology Engineer at Intel Corporation
- Role
- Logic Design Methodology Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Ajay Chandrasekhar
Front-end CAD engineer with experience in micro-architecture design- Experience in L1 D-cache design- Programming skills in C and C++- Scripting skills in Perl and Python- Knowledge of Verilog and SystemVerilog.
Experience
Logic Design Methodology Engineer
Jul 2025 — Present
Enabled and supported design teams with complex XML-based software solution for the specification of control registers in their designs.Developed, enabled and supported design teams with maintenance of their validation plans in Vmanager tool from Cadence, via REST APIs to meet project-specific requirements.
Education
Stony Brook University
Master's degree, Electrical and Computer Engineering
2011 — 2013
Amrita School of Engineering
Bachelor of Engineering, Electronics and Communication
2007 — 2011
Skills
- Drc
- Verilog
- Physical Design
- C
- Programming
- Spyglass
- Cadence Spectre
- Perl
- Cadence Virtuoso
- Digital Circuit Design
- Analog Circuit Design
- Matlab
- Low-Power Design
- Functional Verification
- Systemc
- Logic Design
- Rtl Verification
- Electrical Engineering
- Rtl Design
- Spice
- C++
- Verdi
- Computer Engineering
- Cuda
- Synopsys Tools
- Mips Assembly
- Modelsim
- Systemverilog
- Vhdl
- Lvs
- Computer Architecture
- Rtl Coding
- Computer Hardware
- Microarchitecture
- Vlsi
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