Aishwarya Kawle
Design Verification Engineer at Qualcomm | NC State Graduate
- Role
- Soc Design Verification Engineer at 高通
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Aishwarya Kawle
Working in the field of Digital Design and Verification that enables me to utilize my skills in Functional Verification using System Verilog, UVM Framework and RTL design with Verilog. Skills: • Programming Languages: UVM framework, SystemVerilog, Verilog, C++,Python. • Operating Systems: Windows, Linux • Software tools proficiency: Modelsim, Questasim, Synopsys Design Vision, Visual Studio Summary of Acquired knowledge and skills: 1. In-depth knowledge of Verilog, System Verilog, UVM, constrained random verification 2. Profound knowledge of enforcing test cases and verification methodology 3. Skilled in writing test plans, coverage plans, debugging RTL 4. Experience in designing one full ASIC design cycle from design to synthesis 5. Solid understanding of Functional/Code Coverage, System Verilog Assertions, ASIC Design Flow,logic design and computer architecture concepts 6. Strong Team Work and Communication skills
Experience
Soc Design Verification Engineer
Jul 2020 — Present · San Diego, CA, US
Education
Chaitanya Bharathi Institute Of Technology,Hyderabad
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2013 — 2017
North Carolina State University
Master of Science - MS, Computer Engineering
2018 — 2020
Sri Chaitanya Junior Kalasala,Hyderabad
High School, Maths-Physics-Chemistry
2011 — 2013
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