Aishwary Dadheech

About Aishwary Dadheech

10 years of experience in Physical Domain. Worked on 7nm,16nm,28nm timing closure, STA, Physical verification, IR drop/Power/EM Analysis, functional and timing ECOs, scripting etc. Working on Full Chip Flat/Hierarchical Timing Analysis. Worked as CAD team member for block level IR & EM flow development & Maintenance. Worked on Full Chip Flat/Hierarchical Extraction. Well equipped with ASIC Physical Design (P&R, Netlist to GDSII) Techniques, Flow Automation and Layout Verification. Experience in handling a team effectively. Ability to work simultaneously on multiple blocks/Tasks. Excellent interpersonal skills with abilities to meet deadlines & work under pressure. Good knowledge of scripting languages such as python, perl, tcl, & csh scripting.

Experience

1. Senior Physical Design Engineer

   NVIDIA

   Sep 2021 — Present · Bengaluru, IN

Education

• Sir Padam pat Singhania University,Udaipur

  Bachelor of Technology (B.Tech.)

  2008 — 2012

Skills

• C++
• Digital Signal Processors
• Xilinx
• Rtl Coding
• Verilog
• Physical Design
• Core Java
• I2c
• Asic
• Java
• Uvm
• Open Verification Methodology
• Orcad
• Data Structures
• Eclipse
• Static Timing Analysis
• Digital Electronics
• Synopsys Tools
• Device Drivers
• Amba Ahb
• Functional Verification
• Embedded C
• Rtos
• Vmm
• Primetime
• Simulink
• Microsoft Office
• Vlsi
• Digital Circuit Design
• Robotics
• Microsoft Excel
• Semiconductors
• Operating Systems
• 8051 Microcontroller
• Vhdl
• Visual Basic
• Xilinx Ise
• Pcb Design
• Perl Script
• Perl