Siddharth Upadhyay
M.Tech VLSI & Embedded Systems | RTL Design & FPGA Prototyping | Verilog/SystemVerilog, AXI/PCIe | Interested in AI/ML Hardware Acceleration/TVM & Low-Power Microarchitecture
- Role
- Project Engineer at Manjeera Digital Systems Private Limited
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Siddharth Upadhyay
Project Engineer specializing in high-performance RTL design for ASIC and FPGA…
Experience
Project Engineer
Manjeera Digital Systems Private Limited
Jul 2023 — Present · Hyderabad, IN
Education
Atal Bihari Vajpayee Indian Institute of Information Technology and Management (ABV-IIITM), Gwalior
M.tech
2021 — 2023
Board of Secondary Education, Rajasthan (RBSE)
8th
2008 — 2009
Board of Secondary Education, Rajasthan (RBSE)
10th
2011 — 2012
Rajasthan Technical University, Kota
B.tech
2015 — 2019
Board of Secondary Education, Rajasthan (RBSE)
12th Board
2013 — 2014
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