Ahmed Yehia

About Ahmed Yehia

Emulation and FPGA Prototyping o High performance TLM modeling for Emulation acceleration (UVM acceleration, C/C++, SCEMI pipes) o Verification continuum from Simulation to Emulation and FPGA prototyping o Virtual prototyping (Android/Linux benchmarking on Hybrid Emulation platforms) o Emulation and FPGA prototyping performance optimizations (Synthesis/compile frequency, runtime throughput, turn-around time, time to waveforms).• ASIC/FPGA Digital Design and Functional Verification o Constrained Random/Metric Driven Verification using SystemVerilog, UVM/OVM, Specman-e/eRM. o Assertion Based Verification using SystemVerilog Assertions (SVA). o Logic design using VHDL, Verilog and SystemVerilog. o Simulation performance optimizations and RTL/Gate level functional/timing simulation and Debug.• Low power design and verification o Power strategy definition, verification, simulation and debug using Unified Power Format (UPF) standard. o Power Analysis on RTL and GLE in Simulation/Emulation w/ Power analysis tools (PowerArtist, PowerPro)• On-chip protocols (e.g. AMBA ACE/AXI/AHB/APB). Off-chip protocols (e.g. JTAG, UART, SPI, DDR).• Verification Management and Coverage closure using Accellera Unified Coverage Interoperability Standard (UCIS).• Software Testing & Verification o Black box, white box, negative, Performance/stress, Interactive testing, and test automation.• Platforms: Linux/Unix, SGE/Univa, LSF.• Programming o Shell scripting (Csh, Ksh/Bash), Perl, Python, Tcl, Make, R, C/C++, Java, Android.• Tooling o EDA - Hardware: Veloce/Strato, Veloce Prototyping System (VPS), Zebu Emulation platform o EDA - Software: Questa/Modelsim, VCS, Specman, Verdi, Veloce HYCON, Veloce TBX, Veloce/Questa VIP, Xilinx Vivado, Altera Quartus, Codelink, Questa Infact, Questa CoverCheck, Questa Visualizer o System Level design: Matlab o Source Code Control: Perforce, Git, CVS, Clearcase

Experience

1. Design Verification Engineer

   Apple

   Jan 2020 — Present · Austin, TX, US

Education

• Ain Shams University

  Master's post grad studies, Electronics, Computer SW/HW

  2010 — 2013

• Information Technology Institute (ITI)

  Post Graduate Diploma, VLSI, Electronics Design, Software Programming

  2004 — 2005

• Ain Shams University

  Bachelor's Degree, Electronics and Communications Engineering

  1999 — 2004

Skills

• Systemverilog
• Verilog
• Functional Verification
• Vhdl
• Perl
• Shell Scripting
• Debugging
• Rtl Design
• Soc
• Eda
• Modelsim
• Verification Management
• Open Verification Methodology
• Specman
• Crv, Cdv, and Coverage Closure
• Tcl
• Vlsi
• Uvm
• Tcl-Tk
• Clearcase
• I2c
• Asic
• Pcie
• Fpga
• Ncsim
• Rtl Coding
• Integrated Circuit Design
• Arm
• Computer Architecture
• Dft
• Usb
• Microprocessors
• Low-Power Design
• Simulations
• Mips
• Perl Script
• Amba Ahb
• C
• Code Coverage
• Cvs