Arnab G.

Senior Program Manager @台積電

San Jose, CA, US
MOBILE NUMBERS
+14•••••••92

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WORK HISTORY

Oct 2025 — Present

Senior Program Manager @台積電

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San Jose, CA, US

EDUCATION

N/A

Regional Institute of Technology, Jamshepur (Now N.I.T., Jamshedpur)

B.Sc. (Engineering), Electrical Engineering

N/A

University of Idaho

MS, Computer Engineering

N/A

Institute of Chartered Financial Analysts of India, Hyderabad

CFA, Finance

N/A

ICFAI Business School, Mumbai

PGDBA, Management/Business Administration

SKILLS

Low-Power DesignLogic SynthesisAsicLogic DesignClock Tree SynthesisCircuit DesignPower AnalysisEdaPhysical DesignFloorplanningStatic Timing AnalysisDebuggingRtl DesignTclSocSignal IntegrityRtl CodingVerilogSystem on a Chip (Soc)Integrated Circuit DesignMicroprocessorsSemiconductors

ABOUT ARNAB G.

Management Skills- Lead a geo-diverse team for 3+ years, establishing the Design Services Alliance for Intel Foundry Accelerator- 4+ years of strategic sourcing experience in Design Services domain as a Global Strategic Supply Chain Manager, driving cost, quality, and efficiency improvements- 5+ years of cross-functional program management, driving technical issue resolution and collaboration to meet aggressive product schedules- Delivered on high-level milestones in fast-paced, leading node technology design and solutions engineering- Managed issue resolution within diverse global teams, using data-based decision making- Managed EDA vendor engagement across multiple technology nodes, handling business and technical aspects.Technical Skills- 11+ years of experience in Digital Circuit Physical/Backend Design Flow development & implementation using Intel, TSMC, and NEC technologies- Expertise in custom place and route, bump placement, RDL routing, floorplanning, partitioning, pin assignment, power planning, clock tree synthesis, RC extraction, ECO flow implementation, and full chip integration- Experience with multi-million gate SoCs, high-speed DDR PHY IPs, ASICs, Structured ASICs, and Gate Arrays.

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