Agathya Jagirdar
CPU physical implementation
- Role
- Staff Engineer at 高通
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Agathya Jagirdar
I am a graduate student from German Institute of Science and Technology - TUM Asia…
Experience
Staff Engineer
May 2025 — Present · Hyderabad, IN
Education
Nanyang Technological University Singapore
Master’s Degree, IC Design
2015 — 2017
Keshav Memorial Institute of Technology (JNTUH)
B. Tech, Electronics & Instrumentation Engineering
2008 — 2012
Vasavi Public School (CBSE)
HIGH SCHOOL, Mathematics Social-Science Hindi English
2004 — 2006
RV-VLSI Design Center
Post graduation Diploma, VLSI Backend Design
2012 — 2013
Narayana Junior College
12, Mathematics, Physics & Chemistry
2006 — 2008
Skills
- Static Timing Analysis
- Digital Electronics
- C
- Modelsim
- Virtuoso
- Electronics
- Physical Design
- Synopsys Primetime
- Matlab
- Application-Specific Integrated Circuits (Asic)
- Very-Large-Scale Integration (Vlsi)
- First Encounter
- Vhdl
- Tcl
- Verilog
- Cmos
- Cadence
- Logic Synthesis
- Asic
- Vlsi
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