Sohrab Aftabjahani

Ieee Oregon Computer Society Chair @Ieee-Usa

Portland, OR, US
MOBILE NUMBERS
+15•••••••93

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WORK HISTORY

Dec 2017 — Present

Ieee Oregon Computer Society Chair @Ieee-Usa

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Portland, OR, US

Accepted the Position in Dec 2017 to represent he Computer Society chapter in Oregon ExCom Meetings as the chapter chair. Revitalized (Formally formed) the Oregon Section Computer Society Chapter in August 2019.

EDUCATION

1994 — 1996

University of Tehran

M.S., Electrical and Computer Engineering

2002 — 2011

Georgia Institute of Technology

PhD, Electrical and Computer Engineering

1989 — 1994

Shahid Beheshti University

B.S. , Computer Engineering

SKILLS

UnixSynopsys Design Compiler/TetramaxAlteraSemiconductorsAsicCadCadence VirtuosoSqlModelsimVlsiProgrammingSoftware EngineeringSignal ProcessingMicroprocessorsDigital Testing and Testable DesignMentor Graphics Dft Advisor/Fastscan/Tessent LbistPerlEmbedded SystemsCalibreSpyglassTclCompiler ConstructionSecurityJavaAlgorithmsSynopsys PrimetimeAssembly LanguageSynopsys Vcs-SpecmanDigital Design Validation Methods (Systemverilog, Ovm)AssuraLabviewAutomatic Placement and Routing (Apr)DftParasitic Extraction (Assura, Calibre)Computer ArchitectureSpectreParasitic ExtractionC++Unix Shell ScriptingOperating Systems

ABOUT SOHRAB AFTABJAHANI

Sohrab received a Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2011. Since 2010, he has been with the Intel Corporation contributing to its state-of-art R&D projects in various roles including security expert, staff security researcher, senior DFT engineer, senior digital design and validation engineer, and graphics Integration validation engineer. He joined Intel after 9 years of experience working as software and hardware engineer for TRW and Computer Science Corporation, Telecommunications Research Center, and several electronic system design companies.He is specialized in security, computer-aided design, AI hardware, computer architecture, digital systems, design for test, semiconductor testing, embedded systems, telecommunication systems, software engineering, operating systems, compiler design, and information technology.He is a senior member and serves as the chair of the Oregon section computer society and the chair of the Semiconductor Research Corporation (SRC) Trustworthy and Secure Semiconductors and Systems (T3S) Technical Advisory Board (TAB). He has served as a TAB for the SRC T3S and Computer-Aided Design and Test (CADT) since 2014. He was a 3-time recipient of the SRC Mahboob Khan outstanding liaison award in 2016, 2019, and 2024.He has 40 publications, white papers, technical reports, and book chapters. He has participated actively in scholarly actives (program chair of IVSW, security track chair of MTV workshop, co-organizer of [Intel] Pacific Northwest hardware security workshop) and has reviewed many papers for conferences (DAC, ITC, VTS, AsianHost, TAU, Intel DTTC/SWPC, ICCIT, ICIS, NCM, INC) and journals (TCAD, Proc. of the TODAES, TETC) as well as NSF proposals related to security and design for test. His research interests include the security-related aspects of design, validation, testing, performance analysis of SoCs, making CAD tools security-aware and creating tools to facilitate design for security and security assurance of systems.

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