Aditya Jain
RTL Design Engineer with 16+ years of experience. Passionate about VLSI technology. Excited about learning new areas in VLSI field everyday. Have a curse of curiosity about everything under and beyond the sun.
- Role
- Senior Staff Engineer at Samsung Semiconductor
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Aditya Jain
VLSI Front End Design Engineer, worked in various projects at various stages. Have…
Experience
Senior Staff Engineer
Apr 2024 — Present · Bengaluru, IN
Working as functional leader in peripheral block team which handles SoC peripheral interfaces. Handling a team of IP owners and subsystem owners for SoC design.AMBA (AXI, AHB, APB), I2C, I3C, SPI, UART, flash controller, SMBus etc.
Education
Doctor Bhim Rao Ambedkar University
M.Sc., Electronics
2003 — 2005
Devi Ahilya Vishwavidyalaya
B.Sc., Electronics
2000 — 2003
Vedant, SCL Mohali
Advance PG Diploma, VLSI Design
2005 — 2006
Skills
- Verilog
- Simulations
- Logic Synthesis
- Fpga Prototyping
- Fpga
- Asic
- Debugging
- Eda
- Vlsi
- Integrated Circuit Design
- Systemverilog
- Functional Verification
- Rtl Design
- Soc
- Rtl Coding
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