Garimella Aditya
ASIC IP-RTL Design@ Qualcomm | IP Contributor | BITS Pilani, Goa | NIT, Bhopal
- Role
- Lead Engineer, Senior at 高通
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Garimella Aditya
A computer hardware enthusiast aspiring to kick start career in the field of Digital IC design. Highly interested in CPU, GPU design, Micro architecture, ASIC and SoC design. Pursuing Masters degree in Microelectronics (expected graduation in June 2021) from BITS Pilani, Goa campus. Graduate in Electronics and Communication Engineering from NIT Bhopal, batch of 2018.
Experience
Lead Engineer, Senior
Dec 2025 — Present · Bengaluru, IN
ASIC MicroArch, IP Design for high performance and ultra low power Video Cores.
Education
Maulana Azad National Institute of Technology
Bachelor of Technology - BTech, Electronics and Communication Engineering
2014 — 2018
Birla Institute of Technology and Science, Pilani
Master of Engineering - MEng, MicroElectronics
2019 — 2021
Skills
- Matlab
- Vhdl
- C++
- Teamwork
- Digital Logic Design
- Research
- Spi Interface
- Microcontrollers
- Embedded C
- Data Structures
- Engineering
- Latex
- Universal Asynchronous Receiver/Transmitter (Uart)
- Communication Link Design
- C
- Spice Simulations
- Analog Circuit Design
- Verilog
- Perl Scripting
- Communication
- Cadence Virtuoso
- Digital Circuit Design
- Project Management
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