Aditya Srinivas Vejella
SoC Design Engineer at Intel Corporation
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Aditya Srinivas Vejella
Dynamic Physical Design Engineer with over 9 years of experience at Intel, adept in SoC design and memory circuit design. Demonstrates strong command over netlist to GDS PnR flows, floorplanning, and global clock design. Recognized for exceptional contributions to high-profile projects and technical mentorship. Highly appreciated for developing scripts to ease out tasks, fix critical issues and adapt to any new flows and methodologies.
Experience
Soc Design Engineer
Aug 2018 — Present · IN
PnRFloorplaningGlobal Clocking for Graphics IPLocal ClockingSoC Clock DistributionBalanced Clock Distribution for High Frequency designsClock Tree SynthesisSignal IntegrityTiming AnalysisFormal EquivalenceEM & IRTCL, Perl, Shell
Education
NATIONA INSTITUE OF TECHNOLOGY WARANGAL NIT WARANGAL
M.TECH, ELECTRONICS INSTRUMENTATION
2013 — 2015
SRI VASAVI ENGINEERING COLLEGE
B-TECH, ELECTRONICS
2008 — 2012
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.