Aditya Sinha

About Aditya Sinha

I am a Design Verification Engineer with expertise in SystemVerilog, UVM, and RTL verification for semiconductor products.I bring proven experience in building testbenches, functional coverage models, and debugging complex verification environments.My journey includes working at Micron Technology and contributing to SoC and IP-level verification projects that improved design quality and reduced bug escape rates.I enjoy solving problems creatively, collaborating with cross-functional teams, and delivering results under tight deadlines.Key skills include- Functional & RTL Verification (SystemVerilog, UVM, VCS)- Testbench development, Assertions, Functional Coverage- Debugging, Regression Automation, and Scripting (Python, Perl)- Semiconductor Design Flow, ASIC/SoC VerificationI am passionate about applying verification methodologies to ensure first-silicon success and am eager to connect with professionals in the semiconductor industry. Let’s connect if you are looking for a skilled Verification Engineer who brings both technical expertise and creative problem-solving.

Experience

1. Senior Engineer

   Micron Technology

   Nov 2025 — Present · Hyderabad, IN

Education

• Sri Chaitanya Vidya Niketan

  Senior Secondary

  2015 — 2017

• Bal Vidya Niketan

  Secondary School Certificate

  2014 — 2015

• CV Raman Global University, Bhubaneswar

  Bachelor's degree

  2017 — 2021

• BITS Pilani, Hyderabad Campus

  Master's degree