Aditya Sathe

About Aditya Sathe

Engineering Manager with extensive experience in scalable SOC power management design (RTL through Physical Design), delivering to multiple derivative products. SOC stepping manager driving multiple Tape-Ins. Broad design experience spanning over 14+ years in RTL front end design and physical design, with proven track record over several generations of Intel’s client/mobile CPU products. Key Skills: People Management. Built high performing, motivated team from the ground up. Used effective communication and collaboration to drive large teams of loosely connected stakeholders to develop SOC Power Management designs in highly constrained timelines. SOC Power Management Design – frontend and backend- for SOC designs with FIVR (Fully Integrated Voltage Regulator) as well as platform-VRs. Feature scope management to avoid feature creep, enabling timely completion. High Frequency flop-based and latch-based design, in the Core and Uncore. Expertise in RTL design and microarchitecture development with Verilog/System-Verilog and Synopsys VCS/Verdi. Expertise in Synthesis, Place and Route, Timing Convergence, Timing Constraints, Cross-clock design, multi-voltage design with UPF using Synopsys suite of tools -DC, ICC, Primetime, Spyglass and more. Leveraged unique cross-domain expertise in initiating and driving the effort for conversion of legacy hand-drawn high-frequency custom designs to synthesizable logic.

Experience

1. Director of Engineering

   Qualcomm

   Jun 2024 — Present · Bengaluru, IN

Education

• University of Mumbai

  B.E., Electronics

  1994 — 1998

• Rutgers University

  MS, ECE

  1999 — 2001

Skills

• Design for Test
• Rtl Design
• Processors
• Cmos
• Cadence Virtuoso
• Vlsi
• Vhdl
• Management
• System on a Chip (Soc)
• Tcl
• Verilog
• Low-Power Design
• Engineering Management
• Computer Architecture
• Mixed Signal
• Circuit Design
• Logic Design
• Physical Design
• Systemverilog
• Dft
• Power Management
• Very-Large-Scale Integration (Vlsi)
• Soc
• Application-Specific Integrated Circuits (Asic)
• Timing Closure
• Static Timing Analysis
• Automatic Placement and Routing (Apr)
• Asic
• Logic Synthesis- Snps Dc,Icc,Dp
• Integrated Circuit Design
• Microprocessors
• Eda