Aditya Saimpu
Analog/Mixed-Signal Design Engineer | Expertise in LDO, BGR, PLL | Exposure to Memory Design
- Role
- Design Engineer at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Aditya Saimpu
I am a memory compiler design engineer with around two years of experience working on…
Experience
Design Engineer
May 2025 — Present
Education
Sri Chaitanya College of Education
Junior High/Intermediate
2018 — 2020
Velagapudi Ramakrishna Siddhartha Engineering College
Bachelor of Technology - BTech
2020 — 2024
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