Aditya Maharana

About Aditya Maharana

Hello, I’m Aditya Maharana, currently working as an Analog Layout Design Engineer. I have a strong passion for VLSI (Very Large Scale Integration) and a keen interest in the intricate world of semiconductor design.In my role, I focus on the precise design and layout of analog circuits, ensuring that performance and reliability meet the high standards of today\'s technology. My experience has allowed me to work on challenging projects, honing my skills in circuit layout while continuously learning about the evolving landscape of VLSI.I’m always excited to expand my expertise in semiconductor technology, collaborate with industry professionals, and stay at the forefront of innovation.

Experience

1. Analog Layout Design Engineer

   Texas Instruments

   Jul 2023 — Present · Bengaluru, IN

   Extensive experience in high-speed blocks and critical support cells, including GPIO and ESD protection circuits, with a focus on layout design for high-performance analog and mixed-signal blocks like PLLs, high-speed comparators, and CML circuits at multi-gigahertz frequencies.Proficient in optimizing GPIO cell layouts for digital and analog interfaces, ensuring effective signal routing and minimal parasitics, while also designing and verifying robust ESD protection cells that comply with ESD standards for sensitive high-frequency circuits.Skilled in Cadence Virtuoso, with hands-on experience in DRC, LVS, and parasitic extraction (PEX) to validate layout integrity, while maintaining signal integrity and minimizing EMI and crosstalk to meet performance targets in timing, power, and area.Committed to integrating ESD protection, GPIO functionality, and high-speed design to enhance overall chip performance in advanced semiconductor nodes and eager to take on new challenges in the field.

Education

• NIST University

  Bachelor of Technology - BTech, Electrical and Electronics Engineering

• SRI JHADESWAR HIGH SCHOOL

  MATRICULATION, Engineering Science

• Tara Tarini College, Purushottampur

  INTERMEDIATE, Engineering Science