Aditya Kota
Silicon DFT Manager
- Role
- Asic Dft Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Aditya Kota
A Masters’ graduate in Electronic Engineering (VLSI Design) with 6.3 years of industry experience• Worked as DFT Engineer in Rambus Chip Technologies Pvt.Ltd • Worked as Physical design trainee at RV-VLSI design centre• Team player, quick learner, diligent and good coding, analytical skills.
Experience
Asic Dft Engineer
Jun 2021 — Present · IN
Education
CVSR College of Engineering
Bachelor's Degree, Electrical, Electronics and Communications Engineering
2008 — 2012
SRM University
Master's Degree, VLSI Design
2012 — 2014
Skills
- Boundary Scan
- Asic
- Zero-Delay & Timing Simulations
- Cts
- Cadence Encounter
- Spyglass
- Primetime
- Vhdl
- Cadence Virtuoso
- Logic Design
- Static Timing Analysis
- Linux
- Place & Route
- Coverage Analysis
- Verilog
- Fault Grading
- C
- Programming
- Physical Design
- Drc/Lvs
- Tcl
- Jtag
- Icc Compiler
- Atpg
- Perl
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