Aditya Darak
Power Arch/RTL Design | Qualcomm | Samsung Semiconductors | BITS Pilani
- Role
- Staff Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Aditya Darak
Power Architect / IP Designer Experienced IP and SOC RTL Design Engineer with a demonstrated history of working in the semiconductors industry. Abilities:Power ArchitecturePower Management RTL DesignLow Power, Area / High Performance Architecture designRTL DesignDesign experience of systems based on ARM processorsExperience in CPUs
Experience
Staff Engineer
Dec 2025 — Present · Bengaluru, IN
Education
Birla Institute of Technology & Science, Pilani
Bachelor’s Degree, BE(Hons.) Electrical and Electronics Engineering and MSc(Hons.) Mathematics
2014 — 2019
Skills
- Data Structures
- Research
- C
- Consulting
- Java
- Front-End Development
- Jquery
- Politics
- Public Sector
- Microsoft Office
- Sales
- Algorithms
- Product Development
- Microsoft Excel
- Photoshop
- Leadership
- Autocad
- Public Speaking
- Management
- Javascript
- Microsoft Word
- Web Development
- C++
- Entrepreneurship
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