Aditi Dube
SOC Design Engineer at Intel
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Aditi Dube
6 years of experience in Physical Design on high performance designs. Expertise in Full…
Experience
Soc Design Engineer
Jun 2022 — Present · Bengaluru, IN
Experience working on Intel’3 I3 (7nm) SOC at partition level.• Responsible for working hand-on on multiple partitions including multi-voltage designs for 0p3 exists.• Responsibilities included qualifying the RTL, setting up ADE flow, taking the partitions through APR run and then doing the signoff checks.• Have worked on defining the floorplan, including optimized macro placement, voltage area creation and analyzing the time at all the APR stages.• Have also done LDOP duplication and HTREE creation as a part of CTS closure.• Apart from work, I am part of the group’s fun committee and has hosted group level programs.
Education
Rajiv Gandhi Prodyogiki Vishwavidyalaya
Bachelor of Engineering - BE
2009 — 2013
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