Adithya Deekshith
M.S. Computer Engineering at NC State | TA - UVM | Skilled in Design Verification, RTL Design, UVM, SystemVerilog, and CPU Architecture | Seeking Full-Time Roles
- Role
- Design Verification Engineer at Western Semiconductor
- Location
- Raleigh, NC, US
- LinkedIn followers
- 500 followers
About Adithya Deekshith
Master’s student in Computer Engineering at NC State (Dec 2025) with strong hands-on…
Experience
Design Verification Engineer
Feb 2026 — Present · AZ, US
Developing verification environments for SPI and DMA peripherals using pyuvm and cocotb implementing drivers, monitors, scoreboards and functional coverage to validate protocol compliance, register functionality and corner-case scenarios.Running regressions, debugging RTL through waveform analysis and working with architecture and RTL teams to close coverage.
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