Adithya

About Adithya

Dedicated and outcome-driven Design Verification (DV) professional with 9+ years of experience verifying complex ASICs, FPGAs, and Design IPs across safety-critical and high-performance domains. Strong expertise in SystemVerilog, UVM, Verilog, and VHDL, with deep understanding of design architectures, SoC interconnects, FPGA firmware. Core Expertise: Architecting and developing UVM-based verification environments and UVCs from scratch Driving functional and code coverage closure through effective test planning and coverage analysis Developing BFMs, functional coverage models, SystemVerilog assertions (SVA), and constrained-random testbenches Writing and executing UVM testcases, managing regressions, and debugging spec/design mismatches Strong knowledge of AMBA protocols, including AXI, AHB, and APB in verifying bus interfaces and SoC interconnects. Proficient in Mentor QuestaSim and QuestaSim Visualizer for simulation, coverage, and advanced debug Developing avionics-grade Verification IPs (VIPs), including reference models, scoreboards, and coverage collectors Led verification for avionics FPGA systems achieving 100% requirements traceability and coverage readiness for FAA/EASA SOI-3 audits in compliance with DO-254.Top Skills: UVM • SystemVerilog • Verilog • Functional Verification • DO-254 Compliance • AXI/AHB/APB Protocols • SoC/FPGA Verification • QuestaSim & Visualizer • IBM Rational DOORS

Experience

1. Asic Engineer

   Alpha-Numero Technology Solutions Inc

   Jul 2025 — Present · Endicott, NY, US

   Boeing Integrated Flight Control Electronics – • Integrated full functional coverage for requirements into tests for FPGA verification in the IFCE system using UVM (System Verilog) and QuestaSim• Proactively collaborate with systems and Design teams to address issues related to functional requirements, build failures, RTL/design mismatches during simulation, regression testing, and requirement/design reviews. • Work closely with system architects and RTL designers to close code-coverage gaps by determining whether each gap is due to exclusions, test deficiencies, or specification/Design ambiguities.• Supporting FAA/EASA SOI-3 audits with complete DO-254 verification evidence, traceability, and coverage readiness.

Education

• Global Academy Of Technology

  Bachelor of Engineering (BE), Electronics and Communications Engineering

  2011 — 2015

• PES PU college

  ELECTRONICS

  2009 — 2011