Adhithyan Haridas
Soc Physical Design Engineer @Intel
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WORK HISTORY
Soc Physical Design Engineer @Intel
Toronto, ON, CA
Toronto, Ontario, Canada
EDUCATION
Carleton University
Masters in Electrical and Computer Engineering
SRI KRISHNA COLLEGE OF ENGINEERING AND TECHNOLOGY
Bachelor of Engineering
ABOUT ADHITHYAN HARIDAS
Experienced Physical Design professional with 3+ years of industry expertise. Backed by a master\'s degree focused on VLSI Design. Good knowledge of CMOS fundamentals and Digital Design concepts. Extensive understanding of ASIC Design flow (RTL to GDS). Experience in advanced technology nodes (Intel 18A, TSMC 5nm). In-depth knowledge and understanding of Static Timing Analysis, on-chip variations, and timing parameters. Proficient in complete ASIC backend flow including full chip/tile level STA, block level and Top/Hierarchical Floorplan. Experience in full chip power and bump planning, PnR, Sign-off, and Physical Verification (DRC, LVS). Expertise in writing ECO for timing closure at full chip and tile level. Automation experience including ownership of ASIC Flow from Synthesis to Sign-off. Base silicon-freeze timing analysis and manual ECO. Experience in training new team members in complete ASIC Physical Design flow and other VLSI concepts. Experience with Industry standard EDA Synopsys tools such as Fusion Compiler, ICC2 and Primetime; Cadence tools like Innovus and Virtuoso as well as Siemens EDA tool Calibre. Proficiency in scripting and automation: Shell scripting and TCL.Work Authorization: Canadian Permanent Resident
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