Adarsh Bhupalam
- Role
- Design Verification Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Aug 2020 — Present
Skills
- C
- Verilog
- Csh
- Iccr
- Rtl Design
- Amba Ahb
- Vcs
- Logic Design
- Logic Synthesis
- I2c
- Uart
- Static Timing Analysis
- Synthesis
- Ovm
- Tcl
- Systemverilog
- Functional Verification
- Perl
- Clock Tree Synthesis
- System Verilog
- Linux
- Asic
- Ncverilog
- Synopsys Tools
- Ahb
- Open Verification Methodology
- Rtl Coding
- Physical Design
- Debugging
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