Adarsh Pattanshetty
Layout Engineer Lead
- Role
- Lead Layout Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Adarsh Pattanshetty
Memory Layout Design Engineer with a good history of working in the semiconductors industry. Skilled in Drawing Optimised Layout in 3nm, 4nm, 8nm, 14nm FinFet, 28nm FDSOI, 90nm and 180nm technology nodes, Good in resolving DRC (Design Rule Checking), LVS (Layout v/s Schematics), DFM\'s and EM/IR issues. Strong engineering professional with a Bachelor of Engineering (BEng) focused in Electronics and Communications Engineering (E&C) from Manipal Institute of Technology, Manipal University, Manipal, Karnataka.
Experience
Lead Layout Engineer
Dec 2025 — Present · Bengaluru, IN
Education
Composite Sports English Medium High School,Chandargi-591114
8th,9th,10th, High School
Manipal Institute of Technology, Manipal University, Manipal, Karnataka
Bachelor of Engineering (BEng), Electronics and Communications Engineering (E&C)
Gomatesh Polytechnic Gomatesh Nagar, Hindwadi, Belgaum-590011(Karnataka)
Diploma, Electronics and Communications Engineering (E&C)
RV-VLSI Design Center
Post Graduation Diploma, VLSI
Skills
- Drc
- Verilog
- C
- Cmos
- Embedded Systems
- Microprocessors
- Dfm
- Logic Design
- Very-Large-Scale Integration (Vlsi)
- Vlsi
- Static Timing Analysis
- Xilinx Ise
- Linux
- Modelsim
- Electronics
- Asic
- Systemverilog
- Vhdl
- Lvs
- Cadence
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