Adarsh Chaturvedi
HCLTech | Intel | STMicroelectronics | M.tech in VLSI Design @ NIT Agartala
- Role
- Technology Files Validation and Automation Engineer at HCLTech
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Adarsh Chaturvedi
Currently working @HCLTech as a Design Engineer for techfile development and validation for Intel technology mainly for 22nm, 7nm and 5nm.I had completed my Master\'s from NIT Agartala in VLSI design and done 1 year internship in DRC dec (SVRF) Validation @ STMicroelectronics.
Experience
Technology Files Validation and Automation Engineer
Jun 2024 — Present · IN
Working on development and validation of Tech Files using various layout test cases methodologies and tools like ICV, Cadence Virtuoso, and Custom Compiler for Intel technologies 22nm, 7nm and 5nm, also working on development of automations to reduce mannual efforts in validation using shell and python.
Education
St. Joseph Inter College
Intermediate
NIT Agartala
M.tech [VLSI Design]
2022 — 2024
Vel Tech Technical University
B.tech [Electrical and Electronics Engineering]
2017 — 2021
Vel Tech Rangarajan Dr.Sagunthala R&D Institute of Science and Technology
Bachelor's Degree, Electrical and Electronics Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.