Aditya Jha

About Aditya Jha

To work on a challenging position where I could utilize my hard working and technical skills for the mutual growth and benefit.HDL: VerilogEDA Tool: xilinx ise design tool, Modelsim, familiar with Questasim.Scripting Lang: TCL, PERL, LINUX (bash scripting)Programming Lang: C, C++, Data structureGood knowledge of RTL design, FPGA and ASIC design flow, state machine based design, digital design and Gate Level Simulations

Experience

1. Principal Design Engineer

   Cadence

   Jan 2026 — Present · Bengaluru, IN

Education

• Kurukshetra University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2012 — 2016

• Kurukshetra University

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2012 — 2016

Skills

• Verilog
• Microsoft Word
• Application-Specific Integrated Circuits (Asic)
• C
• Xilinx Ise
• Very-Large-Scale Integration (Vlsi)
• Linux
• Static Timing Analysis
• Digital Electronics
• 8051 Microcontroller
• Cmos
• Leadership
• Matlab
• Public Speaking
• Customer Service
• Rtl Design
• Sta
• Field-Programmable Gate Arrays (Fpga)
• Social Media
• Marketing
• Powerpoint
• Microsoft Excel
• Eda
• Microsoft Office
• Research