Absel Kalarikkal
Senior Staff Engineer at Qualcomm (ASIC digital design)
- Role
- Senior Staff Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Absel Kalarikkal
Working experience in RTL development and IP ownership of various digital designs.Working experience in UPF development (UPF 2.0) for multi power domain subsystem IP.1. Memory controllers2. Inter process communication block3. Sonics\' OCP Fabric4. Synopsys I2C, SPI IPs5. LDO controller (Voltage regulator, digital conrtoller)6. Intel microprocessor subsystem7. Controller Area Network (CAN)8. Protocols - OCP, AMBA (AXI, AHB, APB)Working experience in cluster level IP integration.Hands on experience in digital design tools1. DC (Synopsys), FEV (Conformal)2. QCDC( 0in)(Mentor graphics)3. VCS (Synopss)4. Coretools (Synopsys). Expertise in coretools based subsystem integration and scalability.5. Jasper (Cadence)6. Spyglass-LP (UPF, Low Power), Spyglass-Lint6. Scripting - Perl, Tcl, Perl template toolkit (Scalability)
Experience
Senior Staff Engineer
Dec 2024 — Present
Bluetooth/UWB/Thread(15p4) Baseband Architecture and Digital Design with focus on Packet Processors and Crypto Engines
Education
Government Engineering College Wayanad
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2005 — 2009
National Institute of Technology, Tiruchirappalli
Master of Technology (M.Tech.), Very Large Scale Integration Systems
2010 — 2012
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