Abhishek V
ASIC Physical Design | PDN | EMIR Engineer
- Role
- Asic Design Engineer at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Abhishek V
Full Chip Floor planning includes block partitioning & feed planning. • Hands-on…
Experience
Asic Design Engineer
Jan 2024 — Present
Education
Sathyabama Institute of Science & Technology, Chennai
Bachelor’s Degree
2012 — 2016
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