Abhishek Tandon
Senior Validation Engineer at UST | Masters in VLSI
- Role
- Senior Validation Engineer at UST
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Abhishek Tandon
I am an experienced engineer with a passion for ensuring the quality and functionality of ongoing projects. In my current role as a Core Internal Validator at Intel, I am responsible for running weekly regression tests, writing test case scenarios, and automating the verification process using Python. My experience with tools such as Stargate, Casa Verdi, Comix, VScode, and Jupyter, as well as my hands-on experience with industry-standard verification methodologies like SystemVerilog, has allowed me to make effective contributions to projects in a fast-paced team environment. Additionally, my collaboration with cross-functional teams has helped me hone my communication skills, both verbal and written.Before joining Intel, I worked as a Project Scientist at NIOT, where I managed maintenance of Indian buoy networks, ensuring their optimal performance through calibration, testing, and maintenance of meteorological sensors and subsurface sensors. I also contributed to the development of technical specifications and studied performance to ensure the quality of transmitted data. In addition, I developed innovative projects such as Robofish and Submerged Tsunami Buoy.My experience extends beyond my professional roles. I have also designed and tested an 8-bit RISC processor using Intel Quartus Prime ModelSim and Verilog HDL, and won third prize at a national code-a-thon design challenge. I designed an electronic fish controlled by an FPGA board, which aims to profile the sea in 2 dimensions and capture all the vital sea parameters through a data acquisition system. Additionally, I configured a Memristor-based combinational circuit and compared the result with a CMOS circuit for speed and power.I hold a master\'s degree in VLSI from VIT Vellore and a bachelor\'s degree in ECE from SVIET Patiala. I have a strong skill set in programming languages such as Verilog, System Verilog, Python, TCL, and Perl. I am also familiar with UVM and Cadence Virtuoso. My experience with tools such as Casa Verdi, Stargate, Comix, Jupyter, Linux, Microsoft Power BI, Windows, and VS Code makes me well-equipped to tackle complex engineering challenges.I am a GATE (2021) AIR-1745 qualified engineer and have attended several workshops and training programs, including SoC design using OpenPOWER Cores and virtual workshops on System Verilog high-level synthesis. My publications include \"Remapping of Temperature Profile Measurements in OMNI Buoy Systems\" and \"Sustenance of Indian Moored Buoy Network During COVID-19 Pandemic - A Saga of Perseverance\".
Experience
Senior Validation Engineer
Aug 2023 — Present
Education
Vellore Institute of Technology
Master of Technology - MTech, VLSI
Swami Vivekanand Institute of Engineering & Technology, Banur
Bachelor of Technology - BTech, Electronics & Communication
Skills
- C
- Microsoft Office
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